1. Field of the Invention
The invention generally relates to a method and a circuit for reducing temperature dependence, in particular, to a method and a circuit for generating a clock signal from a clock integrated circuit for reducing temperature dependence of a clock circuit.
2. Description of Related Art
A RC clock circuit may be applied to various integrated circuits for providing a required clock signal. It can be highly integrated with other on-chip components and generally require no external components. FIG. 1A is a circuit diagram illustrating an example of a RC clock circuit 100. In the RC clock circuit 100, a clock trimming resistor R controls a current Ir flowing through a transistor Mr. Transistors M1, M2, and Mr are substantially the same so as to form current mirrors to equalize currents I1, I2, and Ir. The reference voltage Vref is a bias voltage of transistors M1, M2, and Mr and is also used to control alternating charging and discharging of capacitors C1 and C2. Capacitors C1 and C2 have a same capacitance C. A switching stage includes a pair of comparators 130 and 140, a NAND gate 110, a D flip-flop 120, and four switches SW11, SW12, SW21, and SW22. The Comparator 130 compares the voltage Vcap1 of the capacitor C1 with the reference voltage Vref and generates a signal Scmp1 accordingly and the signal Scmp1 is then sent to the NAND gate 110. For example, if the voltage Vcap1 is higher than the reference voltage Vref, the signal Scmp1 is at a high level, otherwise the signal Scmp1 is at a low level. The comparator 140 compares the voltage Vcap2 of the capacitor C2 with the reference voltage Vref and generates a signal Scmp2 accordingly and the signal Scmp2 is then sent to the NAND gate 110. For example, if the voltage Vcap2 is higher than the reference voltage Vref, the signal Scmp2 is at a high level, otherwise the signal Scmp2 is at a low level. The signal S1 output from the D flip-flop 120 is used to enable or disable switches SW11 and SW12. For example, if the signal S1 is at a high level, the switch SW11 is enabled and the switch SW12 is disabled, otherwise the switch SW11 is disabled and the switch SW12 is enabled. The signal S2 output from the D flip-flop 120 is used to enable or disable switches SW21 and SW22. For example, if the signal S2 is at a high level, the switch SW21 is enabled and the switch SW22 is disabled, otherwise the switch SW21 is disabled and the switch SW22 is enabled.
FIG. 1B is a timing diagram illustrating timing of alternating charging and discharging of capacitors C1 and C2 of FIG. 1A. Referring to FIG. 1A and FIG. 1B, it is assumed that, at time of T1 in FIG. 1B, the signal S1 is at a high level and the signal S2 is at a low level, the capacitor C1 is charged to VDD (Vcap1=VDD) immediately for turning on the switch SW11 and turning off the switch SW12, and the capacitor C2 is starting to be discharged from VDD to Vref according to the discharge current I2 for turning off the switch SW21 and turning on the switch SW22. Before the voltage Vcap2 is discharged to Vref, both of the signals Scmp1 and Scmp2 output from comparators 130, 140 are kept high because the voltages Vcap1 and Vcap2 are both higher than Vref, such that no signal transition on the clock input end of the D flip-flop 120, and the signal S1 and the signal S2 are maintained their previous voltage levels. Till the voltage Vcap2 on the capacitor C2 is discharged to Vref (at time of T2 in FIG. 1B), the signal Scmp2 is changed from a high level to a low level and a rising edge occurs on the clock input end of the D flip-flop 120, such that the signal S1 is changed to a low level and the signal S2 is changed to a high level, therefore the capacitor C2 is charged to VDD (Vcap2=VDD) immediately for turning on the switch SW21 and turning off the switch SW22, and the capacitor C1 is starting to be discharged from VDD to Vref according to the discharge current I1 for turning off the switch SW11 and turning on the switch SW12. In this manner, the switching stage alternately charges and discharges the capacitors C1 and C2 between VDD and Vref.
The rate of change of the voltages on the capacitors C1 and C2 between VDD and Vref is referred to one RC time constant T as shown in FIG. 1B and is dominated by the resistance value of the clock trimming resistor R, that is because the transistors M1, M2, and M3 form current mirrors. Referring to FIG. 1A again, the voltage drop ΔV on R is (VDD-Vref) which is equal to the voltage change on the capacitors C1 and C2 while discharging as shown in FIG. 1B, and the discharging current (I1=I2=Iref) can be calculated by ΔV and R, i.e., ΔV/R. Therefore, one RC time constant T can be expressed as below:T(ΔV/R)=C·ΔV  (1)T=C·R  (2)
The clock period of the RC clock circuit equals to two RC time constant (2T) as shown in FIG. 1B. Because the clock period of the RC clock circuit is dominated by R, any variance that occurs on R influences the precision of the clock period. In order to overcome process variation on the clock trimming resistor R, the resistance of the clock trimming resistor R is commonly trimmed to a nominal value after fabrication. However if the clock trimming resistor R is temperature dependent, it could not be adjusted by resistance trimming, such that the clock period of the RC clock circuit drifts accordingly.